Design Verification Engineer - ASIC/UVM/SystemVerilog

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

AMD's Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD's data center product portfolio with a highperformance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.

THE PERSON:

We are seeking a highimpact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, highperformance ASIC designs.
The ideal candidate brings handson verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

You will work in a fastpaced, highly collaborative environment and contribute directly to the success of nextgeneration AMD networking products.

KEY RESPONSIBILITIES:

Verification Architecture & Testbench Development

• Develop robust UVMbased testbench architectures for IP, subsystem, and SoClevel verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and datapath IP.
• Develop highquality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.

Execution, Debug & Closure

• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Rootcause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification signoff methodology.

Tools & Methodology

• Use industrystandard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
• Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).

CrossFunctional Collaboration

• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure highquality deliverables.
• Participate in design reviews, microarchitecture definition, and bring a verification perspective into early design stages.
• Mentor junior engineers and provide technical leadership within the verification team.

LANGUAGES & TOOLS

Required

• Expertlevel knowledge of SystemVerilog and UVM
• Strong handson experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
• Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrainedrandom methodologies
• Strong debug skills across architecture, RTL, and testbench layers
• Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar datapath components
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Preferred

• Experience with performance verification, poweraware verification (UPF), or formal verification
• Familiarity with FPGA/HAPSbased validation and acceleration flows
• Understanding of networking or highspeed I/O pipelines
• Exposure to architectural modeling or C/C++ reference models

PREFERRED QUALIFICATIONS:

• Strong analytical and problemsolving abilities with a proven track record of debugging complex issues
• Ability to lead verification tasks independently and drive crossteam closure
• Excellent verbal and written communication skills
• Comfortable working in a fastpaced, collaborative, multisite environment
• Ability to mentor and guide junior DV engineers

ACADEMIC CREDENTIALS

Bachelor's Degree in Electrical/Computer Engineering or related field, Master's Preferred

#LI-BW1

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.