Senior Distinguished Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

In this role, you will have unmatched technical visibility and the opportunity to drive architectural decisions at the highest levels. You will:

Lead Architectural Vision

• Serve as the principal architect for advanced networking ASICs focused on performance, scale-out capabilities, power efficiency, and silicon leadership.
• Define long-term architectural roadmaps for Marvell's next-gen switching platforms serving AI clusters, hyperscale cloud, carrier, and enterprise markets.

Pioneer Multi-Die and Chiplet Innovation

• Architect multi-die systems, including die-to-die (D2D) high-bandwidth interconnects that redefine how large-scale ASICs are built.
• Champion chiplet-based methodologiesthat increase design modularity, accelerate development cycles, and unlock new product families.

Drive Cross-Functional Systems Thinking

• Partner closely with hardware, software, packaging, validation, and system engineering teams to deliver coherent, system-level solutions.
• Represent the architecture function in executive-level technical reviews and customer engagements.

Elevate Engineering Excellence

• Mentor senior and junior engineers, helping develop the next generation of Marvell's technical leaders.
• Foster a culture of innovation, rigor, and forward-looking design across the organization.

Work Where Innovation Happens

Because this role sits at the core of Marvell's strategic technology engine, it requires full onsite collaboration in Santa Clara-where silicon, system, and architecture teams work side-by-side to accelerate innovation and execution.

What We're Looking For

Educational Background

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field required.
• Master's or Ph.D. strongly preferred.

Experience & Accomplishments

• 15+ yearsof experience in ASIC architecture and design, preferably in networking, switching, or high-performance SoCs.
• Demonstrated leadership in driving complex ASIC or multi-die products from concept through delivery.
• Strong track record of innovation at scale-patents, publications, or industry-recognized contributions.

Technical Mastery

• Deep expertise in:
  • System-level architecture for networking ASICs
  • Multi-die systems and advanced die-to-die protocols
  • Chiplet/heterogeneous integration techniques
  • High-performance switching pipelines, memory subsystems, packet processing, traffic management and buffer management
• Strong understanding of system software interaction, control-plane integration, and full-stack implications.

Leadership & Collaboration

• Exceptional communication and influence skills-able to drive alignment at senior levels.
• Comfortable operating in a fast-paced, highly innovative environment.

Proven mentoring capabilities with a passion for developing engineering talent.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.