New
Principal Silicon Debug Engineer
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![]() United States, Oregon, Hillsboro | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon, Manufacturing and Packaging Engineering (SMPE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Silicon Debug Engineer to join the team.
Responsibilities This is a senior technologist role that will guide Microsoft's strategy and execution on silicon debug, FA/FI and debug tool readiness The candidate should have experience building end to end debug solutions: HW, SW, design collateral procurement, readiness for physical/electrical debug tools and physical FA readiness The position requires someone with experience in semiconductor debug, fault isolation, failure analysis and product engineering yield debugThe candidate will be responsible for developing new silicon debug methodologies for all test content types in our MFG flow The candidate will also be responsible for root-cause of key product issues, circuit marginalities, special circuit failures and translate them into corrective actions in the design, our design methodologies and/or the MFG test flow Successful candidates have deep understanding and experience debugging product issues on ATE and using analytical equipment to isolate failures Deep understanding of best-in class silicon debug tools and methodologies is a must Successful candidates should have strong project leadership skills to manage external vendors, drive cross functional teams and drive sub-project as part of larger development programs |